The field of the invention is planarization and electronic components.
Electronic components are used in ever increasing numbers of consumer and commercial electronic products. Examples of some of these consumer and commercial products are televisions, computers, cell phones pagers, a palm-type organizer, portable radios, car stereos, or remote controls. As the demand for these consumer and commercial electronics increases, there is also a demand for those same products to become smaller and more portable for the consumers and businesses.
As a result of the size decrease in these products, the components that comprise the products must also become smaller. Examples of some of those components that need to be reduced in size or scaled down are printed circuit or wiring boards, resistors, wiring, keyboards, touch pads, and chip packaging.
When electronic components are reduced in size or scaled down, any defects that are present in the larger components are going to be exaggerated in the scaled down components. Thus, the defects that are present or could be present in the larger component should be identified and corrected, if possible, before the component is scaled down for the smaller electronic products.
In order to identify and correct defects in electronic components, the components, the materials used and the manufacturing processes for making those components should be broken down and analyzed. Electronic components are composed, in some cases, of layers of materials, such as metals, polymers, metal alloys, inorganic materials or organometallic materials. The layers of materials are often thin (on the order of less than a millimeter in thickness) and delicate.
As integrated circuits (ICs) become smaller and more advanced as to performance, it is imperative to increase the density of the components on the wafer, while increasing the speed at which the integrated circuit performs its functions. Increasing component density requires, among other things, decreasing the size of the conducting trenches and vias (xe2x80x9cinterconnectsxe2x80x9d) on the wafer. However, decreasing the cross-section of the current-carrying conductor increases the electrical resistance for the same conducting material, which degrades circuit performance and increases heating of the interconnects. Thus, the materials and methods for producing these integrated circuits need to be evaluated and potentially replaced by better performing materials and methods of production.
Conventional IC technology uses tungsten (W) and aluminum (Al) interconnects and/or alloys containing these materials. Both tungsten and aluminum, and alloys thereof, have adequate electrical conductivity for use in electronic components, but future generations of ICs will preferably make use of higher conductivity materials, such as copper (Cu).
Copper has several advantages that make it an ideal material for use in electronic components: a) copper has the highest conductivity of any metal except pure silver, b) copper is readily solderable, c) copper has excellent corrosion resistance in natural environments. Copper alloys are also considered excellent alloys for use in electronic components. Harper, Charles A. ed., Electronic Packaging and Interconnect Handbook, Second Edition, McGraw-Hill (New York), 1997. Copper also has the disadvantage of being diffusivexe2x80x94diffusing easily and widely through other materials typically used in the fabrication of ICs, seriously degrading IC performance. To control copper diffusion into the dielectric material, especially if the dielectric material is porous, barrier materials or layers may be deposited prior to copper deposition (or deposition of any xe2x80x9ccopper-likexe2x80x9d conductive material) to hinder diffusion of copper or another conductive material into the surrounding material or dielectric material.
Once the layered material is prepared, it is planarized to provide a flat, smooth surface that can be patterned and etched with the accuracy required of modern IC components. Contact planarization, such as Chemical Mechanical Planarization (CMP), is known in the art and fully described in textbooks, such as Chemical Mechanical Planarization of Microelectronic Materials, by Joseph M. Steigerwald, Shyam P. Murarka and Ronald J. Gutman (1997). CMP makes use of a polishing pad brought into mechanical contact with a wafer to be planarized with an abrasive slurry interposed between the polishing pad and the wafer. Relative motion (typically rotation) of the polishing pad with respect to the wafer leads to polishing of the wafer through mechanical abrasion. Chemical etching of the wafer then takes place through application of an etching solution to the wafer.
Non-contact planarization, such as Spin Etch Planarization (SEP), is another method of planarization whereby there is no mechanical abrasion of the surface of the wafer. The planarization process takes place purely through application of appropriate chemicals. The process of Spin Etch Planarization is described in U.S. patent application Ser. No. 09/356,487 and is incorporated by reference herein in its entirety. Aspects of non-contact planarization and Spin Etch Planarization have been reported and discussed in the following publications: J. Levert, S. Mukherjee and D. DeBear, xe2x80x9cSpin Etch Planarization Process for Copper Damascene Interconnectsxe2x80x9d in Proceedings of SEMI Technology Symposium 99, Dec. 1-3, 1999, pp. 4-73 to 4-82; J. Levert, S. Mukherjee, D. DeBear, and M. Fury, xe2x80x9cA Novel Spin-Etch Planarization Process for Dual-Damascene Copper Interconnectsxe2x80x9d in Electrochemical Society Conference, October 1999, p. 162 ff; and Shyama P. Mukherjee, Joseph A. Levert, and Donald S. DeBear, xe2x80x9cPlanarization of Copper Damascene Interconnects by Spin-Etch Process: A Chemical Approachxe2x80x9d in MRS Spring Meeting, San Francisco, Calif., Apr. 27, 2000 and Donald S. DeBear, Joseph A. Levert, and Shyama Mukherjee, xe2x80x9cSpin Etch Planarization for Dual Damascene Interconnect Structuresxe2x80x9d in Solid State Technology, March 2000, 43(3), pp 53-60 including all of the references cited in all of the foregoing.
Non-contact planarization suffers from a considerable drawbackxe2x80x94surface defects and imperfections are influenced by the planarization process and portions of the conductive layer in the imperfections or defect are undesirably removed resulting in a dish-like geometry. Dishing is a common and undesirable side effect of removing the field region conductive layer and the barrier layer overlying the field region. In other words, the polishing or planarization procedure wears down the tops of the imperfections but also can wear down the crevices of the imperfections, which results in a surface that contains constant imperfections despite applied planarization techniques.
Therefore, there is a need to improve planarization techniques used in the fabrication of integrated circuits, such that imperfections and surface defects in the conductive layers are not removed or are minimally removed as the surface is being planarized. Further, it is important that the improved planarization techniques do not hinder or disrupt the process of build-up of the integrated circuit.
An electronic component contemplated comprises a) a substrate layer, b) a dielectric material or layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric material or layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer.
The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric material or layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer, which planarizers or can be planarized, to the conductive layer. The protective layer may then be cured to a desirable hardness.
A method of planarizing a conductive surface of an electronic component may comprise a) introducing or coupling a protective layer onto a conductive layer; b) dispersing and planarizing the protective layer across the conductive layer; c) curing the protective layer; d) introducing an etching solution onto the conductive layer; and e) etching the conductive surface to substantial planarity.
Various objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention, along with the accompanying drawings in which like numerals represent like components.